In recent years, development of active matrix display devices such as a liquid crystal display device and a light emitting device has been advancing in response to the demand for its application to mobile devices and the like. In particular, technologies for integrally forming pixel circuits and driver circuits (hereinafter collectively referred to as an ‘internal circuit’) using thin film transistors (Thin Film Transistors; TFTs) formed of polycrystalline semiconductors (poly-Si; polysilicon) formed on an insulator are actively developed. The internal circuit includes a source signal line driver circuit, a gate signal line driver circuit or the like. These driver circuits or the like control the pixel circuits which are arranged in matrix.
In addition, the internal circuit is connected to a controller IC or the like (hereinafter referred to as an ‘external circuit’) through an FPC (Flexible Printed Circuit) and the operation is controlled. Generally, a drive voltage (namely, amplitude of a signal) of an IC used as an external circuit is lower than a drive voltage of an internal circuit in view of reduction in power consumption. At present, an IC which operates at a voltage of 3.3 V is typically used as an external circuit, while a drive voltage of an internal circuit is at 10 V, which is higher as compared to that of the external circuit. Therefore, it is necessary in the case of inputting a signal at 3.3 V from the external circuit to the internal circuit that the amplitude of the signal is converted with a level shift circuit or the like so as to be at around 10 V.
However, in the case of level shifting in the external circuit, such problems arise as an increase of components such as a level shift IC and a power supply IC and an increase in the power consumption. On the other hand, in the case of level shifting in the internal circuit before inputting to a shift register, a data latch circuit or the like, such problems arise as an increase in a layout area and the power consumption or the difficulty of high frequency operation. Therefore, it is required a method for directly inputting a signal having an amplitude of a low voltage from an external circuit to a shift register, a data latch circuit or the like which compose a driver circuit of the internal circuit to obtain an accurate operation (this method is hereinafter referred to as ‘low voltage drive’).
As a driving method of an active matrix display device, there are a digital drive method and an analog drive method. In the case of using the digital drive method, a data latch circuit which samples digital video signals in sequence according to sampling pulses from a shift register is required in the a source signal line driver circuit which compose a internal circuit.
Among data latch circuits, there is the one which deals with an input of a low voltage signal (refer to the following Patent Document 1.).    (Patent Document 1: Japanese Patent Laid-Open No. Hei11-184440)
However, the data latch circuit which deal with an input of a low voltage signal may malfunction due to the influence of variations in the TFT characteristics.
Now, a general conventional data latch circuit is shown in FIG. 2(A). The data latch circuit includes a clocked inverter 2005 and an inverter 2006. The clocked inverter 2005 includes P-channel TFTs 2001 and 2002 and N-channel TFTs 2003 and 2004 all connected in series. The gate electrode of the P-channel TFT 2001 is input with a sampling pulse (LAT) from a shift register while the source electrode have a connecting structure such that a power supply VDD is supplied. The gate electrode of the N-channel TFT 2004 is input with an inverted pulse (LATB) of the sampling pulse (LAT) while the source electrode have a connecting structure such that a power supply VSS is supplied. The gate electrodes of the P-channel TFT 2002 and the N-channel TFT 2003 are input with a digital signal (DATA). In addition, the drain electrodes of the P-channel TFT 2002 and the N-channel TFT 2003 are connected to the inverter 2006.
FIG. 2(B) is a timing chart of the conventional data latch circuit in FIG. 2(A). Operation of the conventional data latch circuit is described with reference to FIGS. 2(A) and 2(B). It should be noted that a digital signal (hereinafter referred to as a ‘data signal’) to be input has a digital format, that is a signal having a potential representing ‘1’ and a potential representing ‘0’. In this specification, the level of the potential representing ‘1’ is referred to as ‘H level’ and a potential representing ‘0’ is referred to as ‘L level’ in any case, regardless of the potential. The potential level satisfies L level<H level unless specially described.
First, in a period T1, the sampling pulse (LAT) at L level is input from a shift register. Then, the LAT is at L level and the LATB is at H level, turning ON the P-channel TFT 2001 and the N-channel TFT 2004. At this time, when the DATA is at H level, the P-channel TFT 2002 is turned OFF while the N-channel TFT 2003 is turned ON, thus the clocked inverter 2005 outputs VSS. On the other hand, when the DATA is at L level, the P-channel TFT 2002 is turned ON while the N-channel TFT 2003 is turned OFF, thus the clocked inverter 2005 outputs VDD.